Electronic equipment may fail not only during operation, but also when it is idle between operational periods. Failures of idle components are referred to as “hidden failures,” because they do not affect service at the moment they occur and thus may go undetected. From the operator's point of view, hidden failures are a particularly troublesome problem, since they may remain undetected until the idle component is activated. In other words, the failure becomes apparent just when the component is actually needed. It is therefore desirable to detect hidden failures while components are idle, so that the failed components can be replaced before they are needed, without interrupting service. Ideally, the idle components should be tested non-intrusively, i.e., without interrupting normal operation of active components.
Backplane-based configurations are commonly used in communication and computing equipment. In network access systems, for example, a backplane may be used to connect a main module, having a trunk link to a core network, to a number of subsidiary modules, such as line cards, with ports serving network users. The main module typically includes a switch for multiplexing among the subsidiary modules. Traces on the backplane connect the subsidiary modules to the ports of the switch. Typically, the main module and subsidiary modules contain embedded processors which are used, inter alia, for self-test and other diagnostic functions.
Various methods are known in the art for self-testing of backplane-based communication equipment. For example, PCT Publication WO 01/93499, whose disclosure is incorporated herein by reference, describes an ATM switch/multiplexer system with non-intrusive self-test capability. A bus couples an ATM layer device (the switch) to a number of physical layer devices. A dedicated self-test circuit also couples to the bus. This circuit is adapted to loop back cells from the ATM layer device in a self-test function through a dedicated virtual circuit.
As another example, U.S. Pat. No. 5,841,788, whose disclosure is incorporated herein by reference, describes methods for backplane interconnect testing. Test vectors are applied to individual circuit boards in a system while the remaining circuit boards are disabled. Backplane faults are identified by comparing observed receiver signals to the signals expected in response to the test vectors.